JELE_V4_N2_RP4 Tamilmani R. Rajesh K. Santhiyakumari N Journal on Electronics Engineering 2249 – 0760 4 2 22 27 TSPC (True Single Phase Clock System), E-TSPC (Extended True Single Phase Clock System) , MTCMOS Technique (Multi-threshold CMOS), DFF (D-Flip Flop), Prescaler, Leakage Power, Speed Performances In this paper, the leakage power and speed performances of extended-true single phase clock and MTCMOS using true single phase clock prescaler are investigated. Based upon this study, MTCMOS technique is implemented in true single phase clock logic DFF design. By using a wired OR logic, only one transistor is used for both mode selection and counting logic system. The working frequency of the counter is enhanced and reduced the critical path between the DFF. Using MTCMOS technique a static leakage power is reduced and the speed performances are improved. The designed counter is compared in term of power consumption using DSCH and Micro wind tools. December 2013 - February 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2622