JELE_V4_N2_RP1 Jayadevi S. Santhiyakumari N. Journal on Electronics Engineering 2249 – 0760 4 2 1 7 Built-In-Self-Test (BIST); Low Power; Single-Input Change (SIC); Test Pattern Generator (TPG) This paper discusses about an efficient Test Pattern Generator (TPG) for built-in self-test. This method generates Multiple Single Input Change (MSIC) vectors in a pattern.A reconfigurable Johnson counter and an accumulator is combined to generate a class of minimum transition sequences. The TPG used in this paper is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also explained to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results shows that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are used. Simulation results with ISCAS benchmarks demonstrates that MSIC can save test power and impose no more than 10% overhead for a scan design. It also achieves the target fault coverage without increasing the test length, and also saves power up to 50%. December 2013 - February 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2619