A 3 GHz 2V Analog PLL at 0.18um CMOS Technology

JELE_V4_N1_RP4 A 3 GHz 2V Analog PLL at 0.18um CMOS Technology N.K. Kaphungkui Ratul Kr Baruah Journal on Electronics Engineering 2249 – 0760 4 1 35 41 Centre frequency, Charge Pump, Phase Lock Loop, Phase Frequency Detector, VCO Kaphungkuiand his co-author Ratul Baruah designed a PLL using 180nm CMOS technology with 2V supply voltage and a low input current of 0.49uA. At the initial stage, three building blocks phase/frequency detector, charge pump and voltage control oscillator are separately simulated and latter combined together to form the PLL as a whole. Tanner software is used in simulationwithout affecting the circuit performance by lowering the supply voltage and scaling the length and width of the CMOS. September – November 2013 Copyright © 2013 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2514