JELE_V2_N4_RP5 V. Saravanan V. Kannan Journal on Electronics Engineering 2249 – 0760 2 4 27 31 Ultra Low Power, 18nm Technology, CNTFET, Nano Device, CMOS This Paper Proposes The Design Of Logic Gates For Ultra Low Power Applications. The Logic Gate Has Been Designed In 18 Nm Technology. In This Paper Carbon Nanotube Field Effect Transistors (Cntfet) Are Introduced For Designing The Digital Circuits. This Paper Presents The Performance Analysis Of Carbon Nanotube Field Effect Transistor (Cntfet), Structure, Types Of The New Nano Device, Operation, And Various Gate Circuit Design Using Cntfet. Results Of The Proposed Design Are Compared With Cmos Based Gates. All The Simulations Are Done In Hspice. June – August 2012 Copyright © 2012 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=1905