JELE_V2_N1_RP8 V. Saravanan M. Vadivel Journal on Electronics Engineering 2249 – 0760 2 1 58 64 Floating Point, Pipelined, Bandwidth This paper presents an algorithm and architecture that facilitate the area-efficient evaluation of arithmetic expressions using deeply pipelined floating-point cores. Due to technological advances, it has become possible to implement floating point cores on FPGAs in an effort to provide hardware acceleration for the myriad applications that require high performance floating-point arithmetic. However, in order to achieve a high clock rate, these floating-point cores must be deeply pipelined. Due to this deep pipelining and the complexity of floating-point arithmetic, floating-point cores use a great deal of the FPGA's area. It is thus important to use as few floating-point cores in architecture as possible. However, the deep pipelining makes it difficult to reuse the same floating-point core for a series of floating-point computations that are dependent upon one another. The results of this study shows the correctness of the algorithm and that the performance achieved is far superior to that of other techniques. Beyond area efficiency, this design has several benefits, including high throughput and a low memory space requirement. Because it only needs to receive one input per clock cycle, it also has a low I/O bandwidth requirement. Because of the low area and the low bandwidth requirement, it is possible to implement multiple copies of the architecture in a single design September - November 2011 Copyright © 2011 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=1585