JELE_V1_N2_RP3 Philemon Daniel Rajeevan Chandel Journal on Electronics Engineering 2249 – 0760 1 2 22 29 Online Testing, Concurrent Test, Offline Testing, Built-in-self-test, Output Vector Monitoring Online concurrent testing of VLSI circuits continues to be a challenge because of the need to test circuits during their normal operation. As offline test techniques and online non-concurrent BISTs cannot be used, new techniques like input vector monitoring concurrent BIST schemes were attempted. But the best of the techniques suffer from major limitations like extremely high concurrent test latency, exponential area overhead, limited fault models and therefore are not a viable solution. In this paper a novel output vector monitoring concurrent BIST scheme is presented. The proposed scheme uses the advantage of an embedded system application and tests only for faults that can occur for the currently loaded application using the run time vectors. This method brings down concurrent test latency to a small fraction, tests for all at-speed fault models, uses a scalable BIST architecture without a noticeable increase in overhead. It eliminates aliasing completely because of double vector compactors. The BIST can also be used for offline concurrent tests which can provide additional coverage to a SBST method. The applicability is validated by implementing the scheme for ALU and decoder in OC8051. To the best of our knowledge the concurrent online BIST using output vector monitoring which works for both online and offline tests is presented for the first time in the open literature. December 2010 - February 2011 Copyright © 2011 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=1368