JELE_V1_N1_RP3
Power Dissipation And Switching Speed Analysis of A CMOS Full Adder In Deep Submicron And Nanoscale Technologies
Manish Kumar
Anwar Hussain
L.L.K. Singh
Journal on Electronics Engineering
2249 – 0760
1
1
21
25
Power Dissipation, Switching Speed, Full Adder, Temperature, Supply Voltage
Design of low power and high speed VLSI circuit has become a necessity for high performance portable devices operated by batteries. In this paper, power dissipation and switching speed of a 1- bit CMOS full adder in deep submicron and nanoscale technologies are analysed. Effects of variations in supply voltage and temperature on power dissipation and switching speed of a CMOS full adder are analysed. MICROWIND and DSCH 3.1 EDA tools are used for the schematic layout and simulation of a CMOS full adder in 0.4micro metre and 90 nm technologies using BSIM4 model.
September - November 2010
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