JELE_V1_N1_RP2 Gargi Khanna Rajeevan Chandel Ashwani Chandel Journal on Electronics Engineering 2249 – 0760 1 1 15 20 Propagation Delay, Crosstalk, Skew, Transition Time In deep submicron technology the performance of VLSI circuits is limited by interconnect rather than device. The nonideal effects viz. delay, power dissipation and cross-talk on the VLSI chips are highly dependent on the global interconnects. For signal integrity the crosstalk and timing constraints are gaining great importance. This paper presents in depth analysis of transition time and skew variation on the crosstalk and delay. It is shown that faster transition time affect behaviour of coupled interconnect lines. All possible input switching patterns are considered for finding worst crosstalk condition. Moreover the impact of temperature is also analysed on the crosstalk and delay. Design results are obtained using SPICE simulations for 70nm and 130nm technology. September - November 2010 Copyright © 2010 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=1194