JEE_V4_N1_RP8 G. Mahesh Manivanna Kumar S. Rama Reddy Journal on Electrical Engineering 2230 – 7176 4 1 51 57 Neutral Point Clamped Inverter, Cascaded Multi Level Inverter This paper presents a multilevel inverter with harmonics reduction along with the reduction in number of switches. The reduction in harmonic content in the three-level neutral-point-clamped (NPC), capacitor clamped inverter with inductive load is obtained by simulation. Similarly the reduction in harmonic content in the cascaded multilevel inverter is obtained. The percentage (%) THD is calculated for various levels (3, 7 and 9 level). Finally the percentage (%) THD obtained from various levels is compared. The functionality verification of the multilevel inverter circuit is done using PSPICE and MATLAB. The harmonic reduction is achieved by selecting appropriate switching angles. July - September 2010 Copyright © 2010 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=1255