JDP_V3_N1_RP6 Alin Mary Varghese Baby Dhanya S.N. Journal on Digital Signal Processing 2322–0368 3 1 30 33 Bilateral Filter, Field–Programmable Gate Array(FPGA), Noise Reduction, Real–Time Processing In this paper a desciption of implementation of a bilateral filter for image denoising. The bilateral filter consists of three components such as a register matrix, a photometric filter and a geometric filter. This design is a kernel based design. The input data is arranged into groups so that internal clock of the design is a multiple of the pixel clock. The bilateral filter is implemented as parallelized pipeline stucture. Kernels of different sizes can be implemented due to the modularity of the filter design and could be done with low effort. Here the bilateral filter is used for color image denoising where it reduces noise as well as preserves the details. There is only negligible quality loss. January - March 2015 Copyright © 2015 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=3288