JDP_V2_N2_RP5 Manish Jaiswal Journal on Digital Signal Processing 2322–0368 2 2 27 30 Least Mean Square (LMS), Field Programmable Gate Array (FPGA), Adaptive Filter A less complex version of Adaptive filter and its architecture is proposed here for high sampling rate and low power consumption. In this paper a small delay approach in adaptive filter is presented as an alternative to simple LMS to reduce the situation of large critical paths in case of high sampling speed applications. In this paper a hardware efficient results (device utilization parameters) are presented. The FPGA families (Artix-7, Virtex-7, and Kintex-7) for low voltage perspective are taken here. Synthesis results shows that artix-7 CMOS family achieves lowest power consumption as 1.118 mW with 83.18 % device utilization. Different Precision strategies like speed optimization and power optimization are imposed to achieve these results. April - June 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2866