JDP_V2_N1_RP4 Manimekalai N. A. Lelinadevi Journal on Digital Signal Processing 2322–0368 2 1 22 25 All-Digital Delay-Locked Loop (ADDLL), All-Digital Phase-Locked Loop (ADPLL) In recent years, Digitally Controlled Delay-Lines (DCDL) is a key block in number of applications and play the role of DAC in traditional circuits. This paper presents a totally glitch free DCDL which overcame the limitation of a NAND based DCDL using strobe control method. Using this logic a clock is presented, that reduces the output jitter when compared to the existing method. The existing method uses a delay control code and reduces the delay of about 40%, but it consumes more power and less area efficient. By using strobe controlled logic, the peak to peak absolute output jitter of 70-80% were reduced. As an example application, All-digital spread-spectrum clock generator (SSCG), All-digital phase-locked loops (ADPLL), Phase-locked loop (PLL) were used. January - March 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2721