JCS_V5_N3_RP4 G. Nandini K. Nagi Reddy Journal on Communication Engineering and Systems 2277-5242 5 3 21 26 I C (or IIC, Inter Integrated Circuit), WishBone, SCL (Serial Clock Line), SDA (Serial Data Line), Master, Slave, Xilinx, Model Sim 6.4a I C Multi Master with Multi Slave is designed from a bidirectional serial data bus containing bidirectional data lines like 2 Serial Data Line (SDL) and Serial Clock Line (SCL) along with Wishbone Signal. I C protocol has the ability to support multiple masters and provides an efficient method of data exchange between devices. This is a very useful protocol for faster devices to communicate each other with slower devices without data loss. With the use of this protocol, a serious problem arises resulting to overlapping of signals. To overcome such problems, a special signal called WishBone signal is used. The main objective of this paper is to observe the operation of the master controller and wishbone controller, which performs high speed data transfer in the presence of master or slave. This yields higher speed data transfer over the network. The complete module is modeled in Verilog HDL and synthesized in Xilinx 13.2i, also simulated in Model Sim 6.4a. May - July 2016 Copyright © 2016 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=8064