JCS_V3_N2_RP5 T. Swarna Latha Suguna Tangimi Journal on Communication Engineering and Systems 2277-5242 3 2 33 39 CMOS Comparator, Low Power, High Speed, Analog-to-Digital Converter and Tanner EDA, Complementary Metal Semiconductor (CMOS) A new CMOS dynamic comparator using dual input, single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to-back inverter in the latch stage is replaced with a dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two crosses, coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, and noise immunity. The simulation results will be shown on the W-Edit; average power consumption is in the T-spice. February - April 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2936