JCS_V2_N3_RP6 Speedy Reminiscence Depiction Scheme Intended For Transmitter And Receiver Parts Of Processors Saisudheer Amba Journal on Communication Engineering and Systems 2277-5242 2 3 47 50 Python, NI-Multisim, Relays, Bipolar Constant Current Sink Today's microprocessors have need to operate at very high IO speed to cater the ever increasing computation need, so characterizing these IO's in a quick efficient and accurate manner is needed for us. The paper involves studying Transmitter( T ) and Receiver ( Rr ) blocks of memory interface of CPU and develop methods to characterized these IO's, X suitable feedback to design is provided after analyzing the data and receiving with design. In this paper involves some analog analysis and design. Here it needs some software tool to implementation. This paper implements new method to increase the speed of the IO operations of the memory interface of CPU. This contain the usage of the NIDAQ6008 and analog design and the circuit design concepts and here it deals with the calculation of the Rterm, Pull-up, Pull-down resistors and Jitter and the de-embedding of the signal loss. May - July 2013 Copyright © 2013 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2336