<article_id>jcir.5.4.13939</article_id>
<article_title>Design and Implementation of Low Power ALU Using 8T Full Adder with FINFETS</article_title>
<author>M. Chandra Sekhar Reddy</author>
<author>P. Ramana Reddy</author>
<journal_title>Journal on Circuits And Systems</journal_title>
<issn>2322–035X</issn>
<volume>5</volume>
<issue>4</issue>
<first_page>8</first_page>
<last_page>14</last_page>
<doi>10.26634/jcir.5.4.13939</doi>
<keywords>FinFET, 8T Full Adder, Arithmetic and Logic Unit, Leakage Power</keywords>
<abstract>An Arithmetic and Logic Unit (ALU) is an advanced circuit that performs number-crunching and rationale operations. ALU is an essential building piece of the focal preparing unit of a PC. The power, devoured by the ALU has a direct effect on the power disseminated from the processor. Thus, a plan is required to execute the ALU in a manner, where the execution of the processor is enhanced and furthermore the power devoured is less. An ALU utilizing 8T Full Adder with FinFETs as a customary technique. In customary, ALU devours a lot of energy. The proposed ALU outlined utilizing 8T Full Adder with a FinFETs. It has an intense control on short channel impacts while downsizing the measure of the transistor. The outline recreation is done in CADENCE IC 12.1 Tool. At long lasting power has been considered and furthermore contrasted between the Exiting ALU plan and proposed FinFET based outline of the ALU.</abstract>
<date>September - November 2017</date>
<copyright>Copyright &copy; 2017 i-manager publications. All rights reserved.</copyright>
<publisher>i-manager Publications</publisher>
<article_url>http://www.imanagerpublications.com/Article.aspx?ArticleId=13939</article_url>