JCIR_V4_N3_RP2 Naman Saxena Shruti Dutta Neeta Pandey Journal on Circuits And Systems 2322–035X 4 3 6 14 PFSCL, Triple-Tail Cell-based PFSCL, FIFO Sequencer, Asynchronous Pipeline, DETFF, C-Muller In this paper, Positive Feedback Source Coupled Logic (PFSCL) based asynchronous pipeline implementation is addressed. Existing Conventional PFSCL and a more efficient Triple-Tail Cell-based PFSCL variant are used for this purpose. Striking a trade-off between both topologies, a new hybrid implementation of the pipeline has been proposed. The concept is elucidated through FIFO sequencer. The hybrid implementation of asynchronous pipeline results in lesser number of gates as well as lower average power dissipation, thus not only making the circuit more efficient but also reducing overall area overhead. The validity of the proposal is confirmed through SPICE simulations using 0.18 um CMOS technology parameters. June - August 2016 Copyright © 2016 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=8219