An Optimized Low Power Self-Resetting Logic Design Approach

JCIR_V4_N2_RP2 An Optimized Low Power Self-Resetting Logic Design Approach Shivani Kulshrestha Vikas Kumar Rai Journal on Circuits And Systems 2322–035X 4 2 17 21 Low Power, Self-Resetting Logic, CMOS This paper presents a new optimized technique to power reduction and performance improvement based on selfresetting logic. The concept of self-resetting logic uses the concept of resetting the output logic automatically after a certain time span. The proposed circuit eliminates the problems of SRLGDI logic proposed previously. SRLGDI was proven to be better than dynamic logic, CMOS self-resetting logic and GDI. Three designs of full adders were made using SRLGDI and a final proposed design was made using modified SRLGDI logic and compared to three SRLGDI designs to prove the performance improvement achieved using the modified SRLGDI logic. March - May 2016 Copyright © 2016 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=8098