JCIR_V4_N1_RP2 K. Rajesh K. Neelima Journal on Circuits And Systems 2322–035X 4 1 12 15 Gain, Time Delay and Noise Figure In modern CMOS technology, the growing demand of low cost integrated circuit requires RFICs featuring low power consumption, high level integration and high data rates, have become critical in wireless systems at around 10 GHz for emerging applications. By employing silicon-based technology it is possible to design low cost direct conversion receivers targeted at 8 - 40 GHz frequency bands. The main focus is on the design and implementation of a receiver front-end for Ka - band (27 - 40 GHz) applications. The drawbacks of these designs are LO self-mixing and 1/f noise. To overcome these drawbacks, a dual - band receiver is proposed to be designed by adopting a wideband two stage LNA and wideband mixer in a 0.18 μm Bipolar Technology. To suppress the LO self-mixing problems, the sub harmonic mixer is applied to the receiver and by adopting a 3D inductor, IF 3-dB bandwidth can be improved. The designs are modeled in SPICE and verified in HSPICE Synopsys tools. December 2015 - February 2016 Copyright © 2016 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=6030