JCIR_V3_N4_RP5
Parallel Prefix Adder Using Static Conventional Logic Gates</author>
<author>D. Divya</author>
<author>M. Bharathi</author>
<author>C. Ruth Vinutha</author>
<journal>Journal on Circuits And Systems</journal>
<issn>2322–035X</issn>
<volume>3</volume>
<issue>4</issue>
<first_page>42</first_page>
<last_page>47</last_page>
<keywords>Asynchronous Circuits, Quasi-Delay Insensitive (QDI) Circuits, Null Conventional Logic (NCL) Gates, Low Power</keywords>
<abstract>An adder is a device, that adds two numbers and generates the summed result. In digital circuits, there are so many adders like carry select adder, ripple carry adder, carry skip adder, ling adder, manchester carry-chain adder and so on. Among all adders, parallel prefix adder is a highly-efficient binary adder. These parallel prefix adders are implemented in a new topology called Static Null Conventional Logic (NCL) gates. NCL gates are asynchronous circuits which are independent of the clock skew problem, delay and consumes less power. The static implementation of conventional versions of NCL gates use a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes while the gate is switching. Implementation of parallel prefix in NCL gates, increase the area overhead problems that occur, but the power consumption reduces due to connecting and disconnecting of the specified gate terminal.</abstract>
<date>September - November 2015</date>
<copyright>Copyright © 2015 i-manager publications. All rights reserved.</copyright>
<publisher>i-manager Publications</publisher>
<article_url>http://www.imanagerpublications.com/Article.aspx?ArticleId=5930</article_url>