JCIR_V3_N1_RP5 Neelima K. Purushotham Prasad Kalisetti Journal on Circuits And Systems 2322–035X 3 1 28 34 SRAM, Lector Technique, Galeor Technique, Deep Submicron Region As the area is shrinking with the scaling of technology, the design of SRAM memory with less leakage power becomes essential for portable devices. Due to the second order effects, the leakage power dominates the static and dynamic power at deep submicron technology. Inspite of applying low power techniques like multi-threshold logic, body biasing techniques, stacked structures etc, the existing SRAM designs at submicron region dissipate more power and become instable. This paper concentrates on low power highly stable single ended SRAM cell design using only seven transistors using Lector and Galeor based low power Techniques. Digital Schematic Tool is used to develop schematics. Microwind Tool is used to develop Layouts at different nanometer technologies. The designs are optimized for low power and good static noise margin. Also the designs are compared for submicron technologies downline from 180nm to 90nm. December 2014 - February 2015 Copyright © 2015 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=3260