<article_id>JCIR_V2_N3_RP2</article_id>
<title>An Efficient Low Power Multiplier Using Subthreshold Adiabatic Logic</title>
<author>Tunga Mounika</author>
<author>Duvvuru Praveen Kumar</author>
<author>Bharathi Muni</author>
<journal>Journal on Circuits And Systems</journal>
<issn>2322–035X</issn>
<volume>2</volume>
<issue>3</issue>
<first_page>7</first_page>
<last_page>11</last_page>
<keywords>VLSI (Very Large Scale Integration), HSPICE (Hewlett Simulation Program with Integrated Circuit Emphasis), CMOS (Complementary Metal Oxide Semiconductor)</keywords>
<abstract>Multiplication Algorithms have considerable effect on processors’ performance. Multiplier is an important circuit used in electronic industry especially in Digital Signal Processing operations such as filtering, convolution and analysis of frequency. There are different types of algorithms used in multipliers to achieve the better performance. In this paper, 8*8 Wallace Tree and Dadda multipliers are implemented using two phase clocking subthreshold adiabatic logic. Its power dissipation is less when compared to their respective 8*8 CMOS multipliers. This paper can be implemented in HSPICE using 0.18μm CMOS standard process technology.</abstract>
<date>June - August 2014</date>
<copyright>Copyright &copy; 2014 i-manager publications. All rights reserved.</copyright>
<publisher>i-manager Publications</publisher>
<article_url>http://www.imanagerpublications.com/Article.aspx?ArticleId=3161</article_url>