This paper explains the implementation based on adaptive filter algorithm with shadow technique, which belongs to the class of LMS algorithm on FPGA. The objective of this paper is to cancel out additive noise due to the effect of environmental conditions in the communication system. The additive noise is one of the major problems in the communication, especially in the digital electronic circuits design these days. Generally, the coefficient of filter updation is not in a basic filter time to time, as it may be an effect on the desired information. By updating coefficient of filter time to time, this problem could be eradicated and by increasing the number of iterations for the filtering process, it would give an efficient result. The popular method used to cancel out the additive noise in the communication systems is the Least Mean Square (LMS) algorithm. Here, a novel shadow based technique is employed in fixed LMS adaptive filter for improving the spectral characteristics like Side Lobe Attenuation (SLA), Main Lobe Width (MLW), Side Lobe Fall of Ratio (SLFR) of the filter by changing the feedback factor 'β'. In this project, it is found that the performance of shadow based fixed LMS is improved when compared to the existed fixed LMS in terms of signal-to-noise ratio (SNR) and Mean Squared Error (MSE) done with the help of MATLAB tool, and this proposed project was implemented on FPGA with utilization of minimum number of logic gates, flip flops, LUT's, and registers that are operated at maximum frequencies. This paper also compares the number of flip flops, logic gates, LUT's, and registers utilized for different resources in the family of FPGA. In real time applications, the adaptive filter algorithm implementation on FPGA plays a crucial role, especially in the DSP processors for effective communication. By introducing the concept of shadow technique in the adaptive filtering, the additive noise would be suppressed in the communication systems. The core FPGA is designed such that, it can be implemented in any brand of SoPC. In this paper, SPARTAN 3E and Vertex 4 are the application platform of FPGA. The achieved results gives an improvement in area resource utilization, convergence rate, speed, and performance in design pure LMS hardware core. Implementing the LMS adaptive filter algorithm on FPGA is achieved in VERILOG hardware description languages.