Design and Analysis of 32x32 Bit ALU using High-Speed Vedic-Wallace Multiplier Based on Vedic Mathematics

Kondu Dharitha Reddy*, P. V. Mahesh**
* PG Scholar, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi, Andhra Pradesh, India.
** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College Tirupathi, Andhra Pradesh, India.
Periodicity:March - May'2016
DOI : https://doi.org/10.26634/jele.6.3.5954

Abstract

This paper is devoted to design a high-speed Arithmetic Logic Unit. All of us know that, ALU is a module which can perform arithmetic and logic operations. The speed of ALU greatly depends upon the speed of the Multiplier. This paper presents a technique called, “Vedic Mathematics” for designing the multiplier that is fast as compared to other multipliers based on mathematical techniques that have been in practice for a long time. Here, a high-speed 32x32 bit multiplier is designed and analyzed which is based on the Vedic mathematics mechanism. The proposed method is efficient and fast, wherein the processing involves the vertical and crossed multiplication of precedent Vedic mathematics. The internal multiplier is implemented using Vedic-Wallace structure for high-speed implementation. The exponent of the final result is obtained by using Brent-Kung adder for fast computations with less area utilization. The projected Vedic multiplier is coded in a High-level Digital Language (VHDL) followed by synthesization using an EDA tool, XilinxISE14.5. The proposed ALU is able to perform three different arithmetic and eight different logical operations at high speed. The main objective of this paper is to increase the speed of the multiplier and to decrease the delay, and area of the hardware.

Keywords

Architecture, Brent-Kung Adder, Vedic Mathematics, Vedic-Wallace (VW), Urdhava Tiryakbhyam Sutra, Arithmetic Logic Unit.

How to Cite this Article?

Reddy, K.D., and Mahesh, P.V. (2016). Design and Analysis of 32x32 Bit ALU using High-Speed Vedic-Wallace Multiplier Based on Vedic Mathematics. i-manager's Journal on Electronics Engineering, 6(3), 7-14. https://doi.org/10.26634/jele.6.3.5954

References

[1]. Garima Rawat, Khyati Rathore, Siddharth Goyal, Shefali Kala and Poornima Mittal, (2015). “Design and Analysis of ALU: Vedic Mathematics”. IEEE Int. Conf. on Computing, Communication and Automation (ICCCA2015), pp. 1372-1376.
[2]. Rahul Nimje and Sharda Mungale, (2014). “Design of arithmetic unit for high-speed performance using Vedic mathematics”. International Journal of Engineering Research and Applications, pp. 26-31.
[3]. Poornima M, Shivaraj Kumar Patil, Shivukumar, Shridhar K P and Sanjay H, (2013). “Implementation of multiplier using Vedic algorithm”. International Journal of Innovative Technology and Exploring Engineering, Vol. 2, No. 6.
[4]. M. Sowmiya, R. Nirmal Kumar, S.Valarmathy and S. Karthick, (2013). “Design of Efficient Vedic Multiplier by the analysis of Adders”. International Journal of Emerging Technology and Advanced Engineering, Vol. 3, No.1.
[5]. Pushpalata Verma and K. K. Mehta, (2012). “Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool”. International Journal of Engineering and Advance Technology, Vol.1, No. 5.
[6]. Abhishek Gupta, Utsav Malviya and Vinod Kapse, (2012). “A novel approach to design high-speed arithmetic logic unit based on ancient Vedic multiplication technique”. International Journal of Modern Engineering Research, Vol. 2, No. 4.
[7]. Suchita Kamble and N. N. Mhala, (2012). “VHDL implementation of 8-bit ALU”. IOSR Journal of Electronics and Communication Engineering, Vol. 1, No. 1.
[8]. Pushpalata Verma, (2012). “Design of 4x4 bit Vedic Multiplier using EDA Tool”. International Journal of Computer Applications, Vol. 48, No. 20.
[9]. Aniruddha Kanhe, Shishir Kumar Das and Ankit Kumar Singh, (2012). “Design and Implementation of Low Power Multiplier Using Vedic Multiplication Technique”. International Journal of Computer Science and Communication (IJCSC), Vol. 3, No. 1, pp. 131-132.
[10]. Umesh Akare, T.V. More and R.S. Lonkar, (2012). “Performance Evaluation and Synthesis of Vedic Multiplier ”. National Conference on Innovative Paradigms in Engineering & Technology (NCIPET-2012), Proceedings published by International Journal of Computer Applications (IJCA), pp. 20-23.
[11]. Anvesh Kumar and Ashish Raman, (2010). “Low Power ALU Design by Ancient Mathematics”. IEEE, 978-1- 4244-5586-7/10.
[12]. Parth Mehta and Dhanashri Gawali, (2009). “Conventional versus Vedic mathematics method for hardware implementation of a multiplier”. International Conference on Advances in Computing, Control, and Telecommunication Technologies, pp. 640-642.
[13]. Ramalatha, M.Dayalan, K D Dharani, P Priya and S Deoborah, (2009). “High speed energy efficient ALU Design using Vedic Multiplication Techniques”. IEEE Int. Conf. on Advances in Computational Tools for Engineering Applications (ACTEA-2009), pp. 600-603.
[14]. Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim and Yong Beom Cho, (2008). “Multiplier design based on Ancient Vedic Mathematics”. IEEE, 978-1-4244- 2599-0/08/$25.00 © 2008.
[15]. Jagadguru Swami Sri Bharati Krishna Tirthji Maharaja, (1986). Vedic Mathematics. Motilal Banarsidas, Varanasi, India.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.