Design of FIR Filter for Efficient FPGA Implementation

S. V. Padmajarani*, 0**
* Professor and HOD, Department of Electronics and Communication Engineering, Sree Venkateswara College of Engineering, A.P, India.
** Principal, Sree Venkateswara College of Engineering and Technology, Chittoor, A.P, India.
Periodicity:March - May'2015
DOI : https://doi.org/10.26634/jele.5.3.3392

Abstract

FIR filters are basic building blocks in Digital Signal Processing applications, require computationally efficient multiply and accumulate operations so the blocks with the desired characteristics have to be chosen carefully. The multiplier is generally slow and occupies large area, the adder also contributes to long delay when the length of the addition is more. Improving the speed results mostly in large areas, usually they conflict with each other. The signal processing applications consume considerable amount of energy. Hence there is a need for low power, high speed, low area circuits for Digital Signal Processing applications. The aim of this paper is to implement a low power, high speed, area efficient FIR filter. Multiply and Accumulate technique is used for multiplier design and the addition and accumulation operations are performed by Parallel Prefix Adders. Some of the available Parallel Prefix Adder architectures and the hybrid architecture of Parallel prefix adder is used here. The implementation is done for 4-tap FIR filter using Xilinx 14.5 version, with the targeted device of Spartan3E FPGA. The experimental results show that the implemented FIR filter using hybrid parallel prefix adder is efficient in area, consume low power and has high speed compared to existing parallel prefix adder models.

Keywords

Digital Signal Processing (DSP), FIR filter, Field Programmable Gate Array (FPGA), High Speed, Look-up Table (LUT), Low Power Consumption, Multiply and Accumulate(MAC), Parallel Prefix Adder (PPA).

How to Cite this Article?

Padmajarani, S.V. , and Muralidhar, M. (2015). Design Of FIR Filter For Efficient FPGA Implementation. i-manager's Journal on Electronics Engineering, 5(3), 1-10. https://doi.org/10.26634/jele.5.3.3392

References

[1]. Actel. Designing FIR Filters With Actel FPGAs, Application Note AC120.
[2]. Atmel. FPGA-based FIR Filter, Application Note, Rev.0529C-09/99.
[3]. Brent, R., & Kung, H. (1982). A regular layout for parallel adders. IEEE Trans, computers, Vol. 31, No. 3, pp. 260-264.
[4]. Chi-JuiChou.,SatishMohanakrishnan., & Joseph B.Evans (1993). FPGA Implementation of Digital Filters.Proc. ICSPAT, pp.1-9.
[5]. Choi, Y, & Swartz lander, EE. (2005). Parallel Prefix th adder design with matrix representation. Proc.17 IEEE symposium on computer Arithmetic (ARITH), pp. 90-98.
[6]. Comoretto, G.(2003). Design of a FIR filter using a FPGA. Arcetri Technical Report, pp. 1-7.
[7]. Cui Guo-wei., & Wang Feng-ying. (2013). “The Implementation of FIR Low-pass Filter Based on FPGA and DA”. IEEE International Conference on Intelligent Control and Information Processing(ICICIP).
[8]. Dawoud, D.S., & Masupa, S. (2006). “Design and FPGA Implementation of Digit-Serial FIR Filters”, South African Institute of Electrical Engineers, AFRICON, Vol. 97, No. 3, pp. 216-221.
[9].Deepak G., P.K.Meher.,& A.Sluzek. (2007). “Performance Characteristics of Parallel and Pipelined Implementation of FIR Filters in FPGA Platform”. IEEE International Symposium on Signals, Circuits and Systems (ISSCS) 2007.
[10]. Dong Shi.,& Ya Jun Yu. (2011). “Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Number of Adders”, IEEE Trans. Circuits and Systems, Vol.58, No. 1, pp. 126-136.
[11]. Dr. Hikmat.,& Abdullah, N. (2008). “Design and Implementation of Programmable FIR filter using FPGA”, Eng.& Tech, Vol. 26, No. 7.
[12]. Fabian Daitx., F.,Rosa,V.S., Eduardo Costa., Paulo Flores.,& Bampi, S. (2008). “VHDL Generation of Optimized FIR Filters”. IEEE International Conference on Signals, Circuits and Systems.
[13]. Ganesh Rao.,& Vineeta. (2011). “Digital Signal nd Processing (Theory and Lab Practice)”, (2 edition), Pearson Education.
[14]. GiorgosDimitrakopoulos & DimitricNikolos. (2005). “High Speed Parallel –Prefix VLSI Ling Adders”. IEEE Trans on computers, Vol. 54, No. 2.
[15]. Giovanni D Aliesio (2003). “8-by-8 Bit Shift/Add Multiplier”, Digital Design and & synthesis COEN 6501, Department of Electrical & Computer Science Engineering, Concordia University.
[16]. Han, T., & Carlson, D. (1987). “Fast area-efficient VLSI th adders”. Proc.8 .symp.Comp.Arit, pp. 49-56.
[17]. Huang, Z. (2003). “High-Level Optimization Techniques for Low-power Multiplier Design”, (Doctoral dissertation). University of California, Los Angeles.
[18]. JianhuaLiuZhu.,Haikun., Chung-Kuan Cheng.,& John Lillis. (2007). “Optimum prefix Adders in a Comprehensive Area, Timing and power Design Space”. Proceeding of the 2007 Asia and South pacific Design Automation conference. Washington, pp. 609-615.
[19]. Kogge, P., & Stone H. (1973). “A parallel algorithm for the efficient solution of a general class Recurrence relations”. IEEE Trans. Computers, Vol. 22, No. 8, pp. 786- 793.
[20]. Ladner, R., & Fischer, M. (1980). “Parallel prefix computation”. J.ACM, Vol. 27, No. 4, pp. 831-838.
[21]. LeventAksoy., Cristiano Lazzari.,Eduardo Costa., Paulo Flores.,& Jose Monteriro. (2013). “Design of Digit- Serial FIR Filters: Algorithms, Architectures, and a CAD Tool”. IEEE Trans. VLSI Systems, Vol. 21, No. 3, pp. 498-511.
[22]. LeventAksoy., Eduardo Costa., Paulo Flores.,& Jose Monteiro. “Minimum Number of Operations under a General Number Representation for Digital Filter Synthesis”.
[23]. Mahesh Kadam., Kishore Sawarkar.,& Sudhakar Mande. (2015). “Investigation of suitable DSP Architecture Efficient FPGA Implementation of FIR Filter ”. IEEE International Conference on Communication, Information & Computing Technology (ICCICT).
[24]. Mohmed al mahdiEshawie., & Masurie Bin Othman. (2008). “An Algorithm Proposed for FIR Filter Coefficient Representation”. International Journal of Mathematics and Computer Sciences. pp. 24-30.
[25]. Narendra Singh Pal., Harjit Pal Singh.,R.K.Sarin., & Sarabjeet Singh (2011). “Implementation of High Speed Fir Filter using Serial and Parallel Distributed Arithmetic Algorithm”, IJCA, Vol. 25, No. 7, pp. 26-32.
[26]. Neil Weste.,& Kamran Eshraghian. (2004). “Principles of CMOS VLSI Design” (2nd edition), Pearson Education.
[27]. Padmajarani, S.V., & Muralidhar, M. (2011). “A Hybrid Parallel Prefix Adder for high speed computing”. Proc. 7th National Conference on Advances in Electronics and Communications(ADELCO).
[28]. Padmajarani, S.V., & Muralidhar, M. (2012). “Design and Implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA”. International Journal of Computer Applications (IJCA), Vol. 58, No. 1, pp. 17-21.
[29]. Padmajarani, S.V., & Muralidhar, M. (2012). “A New Approach to implement Parallel Prefix Adders in an FPGA”. International Journal of Engineering Research and Applications (IJERA), Vol. 2, No. 4, pp.1524-1528.
[30]. Padmajarani, S.V., & Muralidhar, M. (2012). “Comparison of Parallel Prefix Adders Performance in an FPGA”. International Journal of Engineering Research and Development (IJERD), Vol. 3, No. 6, pp. 62-67.
[31]. Pasko, R., Schaumont, P., Derudder, V., Vernalde, S.,& Durackova. D. (1999). “A New Algorithm for Elimination of Common Sub expressions”. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.18, No. 1, pp. 58-68.
[32]. Pramod Kumar Meher. (2010). “New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter”. IEEE Trans. Circuits and Systems, Vol. 57, No.3, pp. 592-603.
[33]. Pramod Kumar Meher., Shruti saga Chandrasekharan., & Abbes Amira. “FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic”. IEEE Trans. Signal Processing, pp.1- 9.
[34]. Raja, L.,Prabhu, B.M., & Thanushkodi, K. (2011). “Design of Low power Digital Multiplier using Dual Threshold Voltage Adder Module”. Elsevier, International Conference on Communication Technology and System Design.
[35]. Ramanathan, p., & Vanathi, P.T. (2009). “A Novel Power Delay Optimized 32-bit Parallel Prefix Adder for High Speed Computing”. International Journal of Recent Trends in Engineering, Vol. 2, No. 6, pp. 58-62.
[36]. RavinderKaur., AshishRaman.,Hardev Singh.,& JagjitMalhotra. (2011). “Design and Implementation of High Speed IIR and IIR Filter using Pipelining”. IJCETE, Vol. 3, No. 2, pp. 292-295.
[37]. Raymon.,& Andraka, J. “FIR Filters Fits in an FPGA using a Bit Serial Approach”, pp. 1-8.
[38]. SabastienBilavarn, Guy Gogniat, Jean-Luc Philippe, & Lilian Bossuet. (2006). “Design Space running Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations”. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 10, pp. 1950- 1968.
[39]. SaeeidTahmasbiOskuii. “Design of Low power reduction Trees in parallel Multipliers”. (Doctoral dissertation). Norwegian University of Science and Technology, Trondheim, Norway.
[40]. SanjitK.Mitra. (2013). “Digital Signal Processing, A th Computer-Based Approach”, (4 edition), Mc.Graw Hill Education.
[41]. SatishMohanakrishnan & Joseph B. Evans. “A Frame for the Design of High Sped FIR Filters on FPGAs”. Telecommunications & Information Sciences Laboratory, University of Kanas, Lawrence, KS 66045-2228.
[ 42].ShahnamMirzaei., Ryan Kastner.,& Anup Hosangadi. (2010). “Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs”. International Journal of Reconfigurable Computing, Vol. 2010, pp.1-17.
[43]. Skalansky, J. (1960). “Conditional sum additions logic”. IRE Transactions, Electronic Computers, EC (9), 226 – 231.
[44]. TaekoMatsunaga, Shinji Kimura,& Yusuka Matsunaga. (2008). “Synthesis of parallel prefix adders considering switching activities”. IEEE International Conference on computer design, pp. 404-409.
[45]. TaekoMatsunaga.,& YusukaMatsunaga. (2007). “Timing-Constrained Area minimization Algorithm for parallel prefix adders”. IEICE TRANS, Fundamentals,E90- A(12).
[46]. Yajun Zhou., & Pingzheng Shi. (2011). “Distributed Arithmetic for FIR Filter implementation on FPGA”. IEEE International Conference on Multimedia Technology (ICMT).
[47]. Yamada. M., & Nishihara. A. (2001). “High Speed FIR Digital Filter with CSD Coefficients Implemented on FPGA”. Proc. IEEE Design and Automation Conference, 7-8.
[48]. Yu-Chi Tsa.,& Ken Choi. (2012). “Area- Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithms”. IEEE Trans. Circuits and Systems, Vol. 59, No. 6, pp. 371-375.
[49]. Zhangwen Tang., Jie Zhang., & Hao Min. (2002). “A High-speed, Programmable, CSD Coefficient FIR Filter”. IEEE Trans. Consumer Electronics, Vol. 48, No. 4, pp. 834- 837.
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