An Efficient Carry Skip Adder Based Reduced Complexity RS-Decoder

Abirsha M*, Amsa Sangara Nayagi. P**
* PG Graduate, Department of Electronics and Communication Engineering, KNSK College of Engineering, Kanyakumari, Tamilnadu, India.
** Assistant Professor, Department of Electronics and Communication Engineering, KNSK College of Engineering, Kanyakumari, Tamilnadu, India
Periodicity:December - February'2015
DOI : https://doi.org/10.26634/jcom.2.4.3330

Abstract

Reed–Solomon (RS) codes are widely used in digital communication and storage systems. In this paper the authors present a high-speed low-complexity Reed–Solomon (RS) decoder architecture using low power carry skip adder. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This reduces the active power. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. A 32-bit carry skip adder is used in the proposed method. Our approach has been implemented in 130 nm CMOS (Complementary Metal Oxide Semiconductor) technology. Compared to the previous designs, the adder architecture decreases the computational complexity with similar or higher coding gain. The 40-bit adder's average power dissipation normalized to 600 MHz operation as 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.

Keywords

Reed–Solomon (RS) Codes, Unified Syndrome Computation (USC), Low Power Carry Skip Adder, Carry Look- Ahead Logic.

How to Cite this Article?

Abirsha, M., and Nayagi, P.A.S. (2015). An Efficient Carry Skip Adder Based Reduced Complexity RS-Decoder. i-manager’s Journal on Computer Science, 2(4), 18-24. https://doi.org/10.26634/jcom.2.4.3330

References

[1]. E. Berlekamp, (1968). “Nonbinary BCH Decoding,” IEEE Transactions on Information Theory, Vol.14(2), pp.242-246.
[2]. R. Koetter and A. Vardy, (2003). “Algebraic Soft- Decision Decoding of Reed–Solomon Codes,” IEEE Transactions on Information Theor y, Vol.49(11), pp.2809–2825.
[3]. J. Bellorado and A. Kavcic, (2006). “A Low-Complexity Method for Chase-Type Decoding of Reed–Solomon Codes,” In Proceedings of IEEE International Symosiyam Information Theory, pp.2037–2041.
[4]. W. J. Gross, F. R. Kschischang, R. Koetter, and P. Gulak, (2002). “A VLSI Architecture for Interpolation in Soft- Decision Decoding of Reed–Solomon Codes,” In Proceedings of IEEE Workshop Signal Processing and Systems, pp.39–44.
[5]. R. Koetter and A. Vardy, (2003). “A Complexity Reducing Transformation in Algebraic List Decoding of Reed–Solomon Codes,” In Proceedings of IEEE Information Theory Workshop, pp.10–13.
[6]. J. Zhu and X. Zhang, (2010). “High-Speed Re-Encoder Design for Algebraic Soft Decision Reed–Solomon Decoding,” In Proceedings of IEEE International Symposiyam on Circuits Sysems, pp.465–468.
[7]. Z. Wang and J. Ma, (2006). “High-Speed Interpolation Architecture for Soft - Decision Decoding of Reed–Solomon Codes,” IEEE Transactions on Very Large Scale Integation (VLSI) Systems, Vol.14(9), pp.937–950.
[8]. X. Zhang, (2006). “Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding,” IEEE Transactions on Very Large Scale Integation (VLSI) Systems, Vol.14( 10), pp.1156–1161.
[9]. J. Zhu, X. Zhang, and Z. Wang, (2009). “Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding,” IEEE Transactions on Very Large Scale Integation (VLSI) Systems, Vol.17(1), pp.1602–1615.
[10]. J. Zhu, X. Zhang, and Z. Wang, (2008). “Combined Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes,” In Proceedings of IEEE Conference on Computer Design, pp.526–531.
[11]. X. Zhang and J. Zhu, (2010). “Algebraic soft-decision decoder architectures for long Reed–Solomon codes,” In Proceedings of IEEE Conference on Computer Design II, Vol.57(10), pp.787–792.
[12]. F. Garcia-Herrero, J. Valls, and P. K. Meher, (2011). “High speed RS (255, 239) Decoder Based on LCC Decoding,” Circuits and Systems Signal Process, Vol.30(6), pp.1643–1669.
[13]. D. V. Sarwate and N. R. Shanbhag, (2001). “High- Speed Architecture for Reed–Solomon Decoders,” IEEE Transactions on Very Large Scale Integation. (VLSI) Systems, Vol.9(5), pp.641–655.
[14]. X. Zhang and J. Zhu, (2010). “Reduced-Complexity Multi-Interpolator Algebraic Soft-Decision Reed–Solomon Decoder,” In Proceedings of IEEE Workshop Signal Processing and System, pp.398–403.
[15]. J. Zhu and X. Zhang, (2009). “Factorization-Free Low Complexity Chase Soft-Decision Decoding of Reed–Solomon Codes,” Circuits and Systems Signal Process, pp. 2677–2680.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.