FPGA Based Fault Tolerance and Recovery Process in Digital Systems Using Genetic Algorithm

P. Renugadevi*, R. Jeyanthi**
* Student, K.S.Rangasamy College of Engineering, Tiruchencode, Nammakal.
** Assistant professor, K.S.R College of Engineering, Tiruchencode, Nammakal.
Periodicity:May - July'2014
DOI : https://doi.org/10.26634/jes.3.2.3202

Abstract

In recent times self-repairing digital systems have emerged as the most favorable alternative for fault-tolerant systems. However, such systems are still unrealistic in many cases, predominantly due to the complex rerouting process that follows cell replacement. They lose efficiency when the circuit size surges, due to extra hardware besides the functional circuit and the non-utilization of normal operating hardware for fault recovery. In Endocrine cellular communication, when an endocrine cell dies in a specific process, the collection of cells and tissues of an organism secretes a hormone and its connections are maintained through blood vessels. Inspired by this communication process, a system has been proposed which reduces hardware overhead to maintain good fault coverage. A fault recovering system is proposed by the use of genetic algorithm to increase the lifetime of the digital circuits. Genetic Algorithms are often expected to design combinational circuits with the fault-tolerant and self-repair ability, Spare cells are used as a replacement in case of failures occurring in working cells. Comparing with the existing methods, the mechanism proposed will be efficient for the real fault tolerant systems.

Keywords

Self Repairing, Spare Cells, Working Cell, Genetic Algorithm

How to Cite this Article?

Renugadevi.P., and Jeyanthi.R. (2014). FPGA Based Fault Tolerance And Recovery Process In Digital Systems Using Genetic Algorithm. i-manager's Journal on Embedded Systems, 3(2), 1-8. https://doi.org/10.26634/jes.3.2.3202

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