FPGA Realisation Of An Optimal Reed Solomon Encoder

P. Ratna Kamala*, R. V. S. Satyanarayana**
* Assistant Professor, EIE, Sree Vidyanikethan Engg College, Tirupati.
** Professor, ECE, SV University, Tirupati.
Periodicity:January - March'2014
DOI : https://doi.org/10.26634/jwcn.2.4.2650

Abstract

The demands of achieving data integrity during transmission through coding over a wireless network have continued over time due to the high volume of data exchanged. This paper proposes an implementation of Reed Solomon code which is one of the Linear block codes that has been found to be optimal for reliable data transmission with its optimum parameters as n=255 and K=223. This optimum Reed Solomon encoder /decoder, RS(255,223) is implemented with Verilog description for Encoder and VHDL description for Decoder. This paper emphasizes on FPGA (Field Programable Gate Array) prototyping of the RS (255,223) encoder with less utilization of Hardware resources.

Keywords

Galios Field, RS (Reed Solomon Code), FPGA (Field Programable Gate Array) , Verilog, Error Correction & Detection

How to Cite this Article?

Kamala, P.R., and Satyanarayana, R.V.S. (2014). FPGA Realisation of An Optimal Reed Solomon Encoder. i-manager’s Journal on Wireless Communication Networks, 2(4), 27-32. https://doi.org/10.26634/jwcn.2.4.2650

References

[1]. Military Handbook,”Reliability prediction of Electronic Equipment”: MIL-HDBK-217F.
[2]. Texas Instruments TTL Logic Data Book. 1988. pp. 2-10.
[3] Wakerley, J.F. (1990).: Digital Design of Principles and Practice, Prentice-Hall,
[ 4 ] . Andrea Goldsmith , (2005 ) .” Wireless Communications”, Cambridge University Press,
[5]. Gallager, Robert G. (1972). Information Theory and Reliable Communication,. Wein: Springer- Verlag, Print.
[6]. Jorge castineira moreire & Patrick Guy Farrell, (2006). “essentials of error control coding”, John Wiley & Sons Ltd,
[7]. W.Cary Huffman & Vela Pless (2003). Fundamentals of Error Correcting Codes, Cambridge University Press,
[8]. 74F401 CRC Generator/Checker, Fair Child semiconductors,1999.
[9]. AFIT/GE/ENG/88D-20, Hardware Implementation of A BCH Encoder, Decoder Thesis, AIR Force Institute of Technology,Ohio.
[10]. AHA Applications Note, "Primer: Reed Solomon Error Correction Codes (ECC)." Advanced Hardware 597 to 2- 599.Architectures Inc., 2365 NE Hopkins Court, Pull man, WA 99 163-5601.
[11]. Blahut, Richard E. (1983). Theory and Practice of Error Control Codes. Reading, MA: Addison- Wesley Pub., Print.
[12]. C. K. P. Clarke, (2002). “Reed-Solomon error correction,” BBC R&D White Paper, WHP 031.
[13]. “Reed-Solomon (RS) Coding Overview,” VOCAL Technologies, Ltd., Rev. 2.28n.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.