References
[1]. Feng Liang, Luwen Zhang, Shaochong Lei, Guohe
Zhang, Kaile Gao, and Bin Liang, (2013). "Test Patterns of
Multiple SIC Vectors: Theory and Application in BIST
Schemes," IEEE Transactions On Very Large Scale
Integration (VLSI) Systems, Vol. 21, No. 4.
[2]. A. Abu-Issa and S. Quigley, (2009). "Bit-swapping LFSR
and scan-chain ordering: A novel technique for peakand
average-power reduction in Scan-based BIST," IEEE
Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 28,
No. 5, pp. 755–759.
[3]. S. Wang and S. Gupta, (2006). "LT-RTPG: A new testper-
scan BIST TPG for low switching activity," IEEE Trans.
Comput.-Aided Design Integr.Circuits Syst., Vol. 25, No. 8,
pp. 1565–1574.
[4]. S. Bhunia, H. Mahmoodi, D. Ghosh, S.
Mukhopadhyay, and K. Roy, (2005). "Low-power scan
design using first-level supply gating," IEEE Trans.Very Large
Scale Integr. (VLSI) Syst., vol. 13, No. 3, pp. 384–395.
[5]. P. Girard, (2002). "Survey of low-power testing of VLSI
circuits," IEEE DesignTest Comput., Vol. 19, No. 3, pp.
80–90.
[6]. S. Wang and S. Gupta, (2002). "DS-LFSR: A BIST TPG for
low switching activity," IEEE Trans. Comput.-Aided Design
Integr. Circuits Syst., Vol. 21, No. 7, pp. 842–851.
[7]. P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch,
and H. Wunderlich, (2001). "A modified clock scheme for
th a low power BIST test pattern generator," in Proc. 19 IEEE
VTS VLSI Test Symp., pp. 306–314.
[8]. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S.
Pravossoudovitch, (2001). " A gated clock scheme for low
power scan testing of logic ICs or embedded cores," in
th Proc. 10 Asian Test Symp., pp.253–258.
[9]. F. Corno, M. Rebaudengo, M. Reorda, G. Squillero,
and M. Violante, (2000). "Low power BIST via non-linear
th hybrid cellular automata,"in Proc. 18 IEEE VLSI Test Symp,
pp.29–34.
[10]. X. Zhang, K. Roy, and S. Bhawmik, (1999).
"POWERTEST: A tool for energy conscious weighted
th random pattern testing," in Proc. 12 Int. Conf.VLSI Design,
pp. 416–422.
[11]. P. Girard, L. Guiller, C. Landrault, and S.
Pravossoudovitch, (1999). "A test vector inhibiting
th technique for low energy BIST design," in Proc. 17 IEEE VLSI
Test Symp. 407–412.
[12]. F. Corno, M. Rebaudengo, M. Reorda, and M.
Violante, (1999). "A new BIST architecture for low power
circuits," in Proc. Eur. Test Workshop, pp. 160–164.
[ 1 3 ] . P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, and
M. Santos, (1999). "Low-energy BIST design: Impact of the
LFSR TPG parameters on the weighted switching activity,"
In Proc. IEEE Int. Symp. Circuits Syst., Vol. 1. Jul. pp.
140–143.
