References
[1]. International technology roadmap to semiconductors, ITRS. Website: ttp://public.itrs.net. (2009).
[2]. D. B. Jarvis, (1963). “The effects of interconnections on high speed logic circuits,” IEEE Trans. on Electronic Computers, Vol. 10, pp. 476-487, 1963.
[3]. Y. I. Ismail, E. G. Friedman, and J. L. Neves, (1999). “Figures of merit to characterize the importance of on-chip inductance,” IEEE Trans. on VLSI Systems, Vol. 7, pp. 442-449, 1999.
[4]. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, (2003). Digital Integrated circuits-A design Perspective, 2nd ed. (Prentice Hall Electronics and VLSI Series, NJ: Pearson Education ) 2003.
[5]. R. Chandel, S. Sarkar, and R. P. Agarwal, (2007). “Delay and power management of voltage-scaled repeaters for long interconnects,” International Journal of Modelling & Simulation, ACTA Press, Vol. 27, pp. 333-339, 2007.
[6]. H. B. Bakoglu and J. D. Meindl, (1985). “Optimal interconnection circuits for VLSI,” IEEE Trans. Electron Devices, Vol. 32, pp. 903-909, 1985.
[7]. V. Adler and E. G. Friedman, (1998). “Repeater design to reduce delay and power in resistive Interconnect,” IEEE Trans Circuits Syst. II, Vol. 45, pp. 607-16, 1998.
[8]. R. Chandel, S. Sarkar, and R. P. Agarwal, (2007). “An Analysis of interconnect delay minimization by low-voltage repeater insertion,” Microelectronics J. Elsevier Science, Vol. 38, pp. 649-655, 2007.
[9]. K. Banerjee, and A. Mehrotra, (2001). “Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling,” Proc. IEEE Symp. VLSI Circuits, Kyoto, Japan, pp. 195-198, 2001.
[10]. R. Chandel, S. Sarkar, and R. P. Agarwal, (2005). “On mitigating power and delay in VLSI interconnects,” IEEE Canadian Conf. on Electrical and Computer Engineering, pp. 1533-1536, 2005.
[11]. P. Maffezzoni and A. Brambilla, (2000). “Modeling delay & crosstalk in VLSI interconnect for electrical simulation,” Electronics Lett., Vol. 36, pp. 862-864, 2000.
[12]. J. A. Davis and J. D. Meindl, (2000). “Compact distributed RLC interconnect models-Part II. Coupled line transient expressions and peak crosstalk in multilevel interconnect networks,” IEEE Trans. on Electron Devices, Vol. 47, pp. 2078-2087, 2000.
[13]. K. Agarwal, D. Sylvester and D. Blaaw, (2006). “Modeling and analysis of cross talk noise in coupled RLC interconnects,” IEEE Trans. CAD of Integrated Circuits and Systems, Vol. 25, pp. 892-901, 2006.
[14]. D. Sylvester, C. Hu, O. S. Nakagawa and S. Y. Oh, (1998). “Interconnect scaling: signal Integrity and performance in future high speed CMOS design,” IEEE Sym. on VLSI Technology Digest of Technical Papers, pp. 42-43, 1998.
[15]. B. K. Kaushik, S. Sarkar, R. P. Agarwal, and R. C. Joshi, (2006). “Cross-talk analysis and repeater insertion in interconnects,” Microelectronics International, Vol. 23, pp. 55-63, 2006.
[16]. G. Khanna, P. Sharma, R. Chandel, and S. Sarkar, (2008). “Cross-talk mitigation in coupled VLSI interconnects,” Proc.12th IEEE Sym. on VLSI Design and Test, Bangalore, India, pp. 364-374, 2008.
[17]. K. T. Tang and E. G. Friedman, (1999). “Interconnect coupling noise in CMOS VLSI circuits,” Proc. International Sym. on Physical Design ISPD, California, United States, pp. 48-53, 1999.
[18]. MOSIS Service for HSPICE models. Online: http://www.mosis.org, 2007.
[19]. N. Delorme, M. Belleville, and J. Chilo, (1996). “Inductance and capacitance analytic formulas for VLSI interconnects,” Electron Letter, Vol. 32, pp. 996-997, 1996.
