References
[1]. Appenzeller J (2008). “Carbon Nanotubes for High-
Performance Electronics Progress and Prospect ”,
Proceedings of the IEEE, Vol. 96, No. 2, pp. 201-211.
[2]. Postma H, Teepen T, Yao Z et al. (2001). “Carbon
Nanotube Single-Electron Transistors at Room
Temperature”, Science, Vol. 293, No. 5527, pp. 76-79.
[3]. Kurt A. Moen (2010). “Evaluating the Influence of
Various Body-Contacting Schemes on Single Event
Transientsin 45-nm SOI CMOS” IEEE Transactions on
Nuclear Science, Vol. 57, No. 6, pp 3366 – 3372.
[4]. Kyung Ki Kim (2010). “On-Chip Aging Sensor Circuits
for Reliable Nanometer MOSFET Digital Circuits” IEEE
Transactions on Circuits and Systems, Vol. 57, No. 10, pp
798 – 802.
[5]. Davide Ponton (2009). “Design of Ultra-Wideband
Low-Noise Amplifiers in 45-nm CMOS Technology:
Comparison Between Planar Bulk and SOI FinFET Devices”,
IEEE Transactions on Circuits and Systems, Vol. 56, No. 5,
pp 920 – 932.
[6]. Radosavljevic, M. et al. (2003). “Drain Voltage
Scaling in Carbon Nanotube Transistors” Appl. Phys. Lett.,
Vol. 83, No. 12, p. 2435-2437.
[7]. Pecchia, A. et al. (2003). “Electronic Transport
Properties of Molecular Devices”, Physical Review Letters,
Vol. 19,pp. 139-144.
[8]. Kyung Ki Kim, Yong-Bin Kim, Ken Choi (2011).“Hybrid
CMOS and CNFET Power Gating in Ultralow Voltage
Design” IEEE Transactions on Nanotechnology, Vol. 10,
No. 6, Pp 1439-1448.
[9]. Li J, Zhang Q, Yan Y et al. (2007). “Fabrication of
Carbon Nanotube Field-Effect Transistors by Fluidic Alignment Technique”, IEEE Transactions on Nano-
Technology, Vol. 6, No. 4, pp. 481-484.
[10]. Bachtold A, Hadley P, Nakanishi T and Dekker (2001).
“Logic Circuits with Carbon Nanotube Transistors”,
Science, Vol. 294, No. 9, pp. 1317-1320.
[11]. Chen Z, Appenzeller J, Lin Y-M et al. (2006). “An
Integrated Logic Circuit Assembled on a Single Carbon
Nanotube”, Science, Vol. 311, No. 5768, p. 1735.
[12]. Rahman A, Jing Guo, Datta S and Lundstrom M S.
(2003). “Theor y of Ballistic Nanotransistors”, IEEE
Transactions on Electron Devices, Vol. 50, No. 10, pp.
1853-1864.
[13]. Raychowdhury, A. and Roy, K. (2005), “Carbon
Nanotube-Based Voltage-Mode Multiple-Valued Logic
Design”, IEEE Trans. Nanotechnology, Vol. 4, No. 2, pp.
168-179.
[14]. Han, J. and Jonker, P. (2002). “A System Architecture
Solution for Unreliable Nanoelectronic Devices”, IEEE
Trans. Nanotechnology, Vol.1, pp. 201-208.
[15]. Heinze S et al. (2002). “Carbon Nanotubes as
Schottky Barrier Transistors”, Physical Review Letters, Vol.
89.
[16]. Ian O'Connor, Junchen Liu, et al (2007). “CNTFET
Modeling and Reconfigurable Logic-Circuit Design” IEEE
Transactions on Circuits and Systems, Vol. 54, No. 11, pp
2365-2379.
[17]. Khairul Alam, Roger Lake, l (2007). “Role of Doping in
Carbon Nanotube Transistors With Source/Drain
Underlaps” IEEE Transactions on Nanotechnology, Vol. 6.
[18]. Youngki Yoon, James Fodor, and Jing Guo, (2008).
“A Computational Study of Vertical Partial-Gate Carbon-
Nanotube FETs” IEEE Transactions on Electron Devices,
Vol.55, No. 1.
[19]. J. Liu, I. O'Connor, D. Navarro, F. Gaffiot (2007).
“Design of a Novel CNTFET- based Reconfigurable Logic
Gate” IEEE Computer Society Annual Symposium on
VLSI(ISVLSI'07).
[20]. Jie Deng, H.-S. Philip Wong (2007). “A Compact
SPICE Model for Carbon- Nanotube Field-Effect Transistors
Including Nonidealities and Its Application Model of the Intrinsic Channel Region” IEEE Transactions on Electron Devices, Vol. 54, No. 12, Pp 3186-3194
[21]. Deji Akinwande, Yoshio Nishi,and H.S. Philip Wong,
(2008). “ An Analytical Derivation of the Density of States,
Effective Mass, and Carrier Density for Achiral Carbon
Nanotubes” IEEE Transactions On Electron Devices, Vol.
55, No. 1, Pp 289 – 297.
[22]. Jie Deng, H.-S. Philip Wong, (2007). “A Compact
SPICE Model for Carbon- Nanotube Field-Effect Transistors Including Nonidealities and Its Application” IEEE
Transactions On Electron Devices, Vol. 54, No. 12, Pp 3195
– 3205.
[23]. Arijit Raychowdhury, Saibal Mukhopadhyay,
andKaushik Roy (2004). “Circuit- Compatible Model of
Ballistic Carbon Nanotube Field-Effect Transistors” IEEE
Transactions on Computer-Aided Design of Integrated
Circuits and Systems, Vol. 23, No. 10, pp 1411–1420.
