In digital VLSI design calculation of setup/hold time is very important part. Setup/hold time defines the maximum speed of the circuit on which it can work. When a design is completed the first step is to check the timing performances of circuit using Static Timing Analysis (STA) (Scheffer et al., 2006). Accuracy of STA depends on the data described in standard cell libraries. So accuracy of STA depends on accuracy of standard cell library characterization (Cirit, 1991; Roethig, 2003; Patel, 1990; Phelps, 1991). As the technology is scaling down, the characterization of standard cell libraries are becoming more time consuming and requires large computational time. Further due to process, voltage and temperature (PVT) variations standard cell library characterization is done for various PVT, this increase characterization greatly. In this paper we present a novel approach to speed up standard cell library characterization for true single phase clocked (TSPC) latch (Yuan and Svensson, 1989) setup time by developing a linear setup time model. In this model setup time varies linearly with output load capacitance (CL) and input transition time (TR). We express setup time model coefficients as a function of logic gate size (Wn) of the latch. We do not use device current/capacitance models in derivation of model, so it is valid with technology scaling. Using proposed model approximately 70% SPICE simulation during the standard cell library characterization for latch setup time can be saved. We observed that setup time calculated using proposed model is within 2% (average) of that calculated using simulation.
