Variation of Crosstalk with Transition Time and Skew on Global VLSI Interconnects

Gargi Khanna*, Rajeevan Chandel**, Ashwani Chandel***
*-** Department of Electronics & Communication Engineering, NIT Hamirpur, India.
*** Department of Electrical & Electronics Engineering, NIT Hamirpur, India.
Periodicity:September - November'2010
DOI : https://doi.org/10.26634/jele.1.1.1194

Abstract

In deep submicron technology the performance of VLSI circuits is limited by interconnect rather than device. The non-ideal effects viz. delay, power dissipation and cross-talk on the VLSI chips are highly dependent on the global interconnects. For signal integrity the crosstalk and timing constraints are gaining great importance. This paper presents in depth analysis of transition time and skew variation on the crosstalk and delay. It is shown that faster transition time affect behaviour of coupled interconnect lines. All possible input switching patterns are considered for finding worst crosstalk condition. Moreover the impact of temperature is also analysed on the crosstalk and delay. Design results are obtained using SPICE simulations for 70nm and 130nm technology.

Keywords

Propagation delay, Crosstalk, Skew, Transition time

How to Cite this Article?

Gargi Khanna, Rajeevan Chandel and Ashwani Chandel (2010). Variation of Crosstalk with Transition Time and Skew On Global VLSI Interconnects. i-manager’s Journal on Electronics Engineering, 1(1),15-19. https://doi.org/10.26634/jele.1.1.1194

References

[1]. International technology roadmap to semiconductors, Website: http://www.itrs.net/Links/ 2009ITRS/2009 Chapters_2009 Tables /2009_ Interconnect.
[2]. J. M. Rabaey, A. Chandrakasan and B. Nikolic. (2002). Digital Integrated Circuits, 2nd ed., Prentice Hall India.
[3]. H.B. Bakoglu. (1990). Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Reading, MA.
[4]. R. Chandel (2005). Study of voltage-scaled repeaters for long interconnects in VLSI circuits, PhD thesis, IIT, Roorkee.
[5]. J.A. Davis and J.D. Meindl. (2000). “Compact distributed RLC interconnect models—part II: Coupled line transient expressions and peak crosstalk in multilevel interconnect networks,” IEEE Trans. Electron Devices, Vol. 47, No. 11, pp. 2078-2087, Nov.
[6]. K. Agarwal, D. Sylvester, and D. Blaaw. (2006). “Modeling and analysis of cross talk noise in coupled RLC interconnects,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 5, pp. 892- 901.
[7]. A. Nieuwoudt, J. Kawa and Y. Massoud. (2010).“Crosstalk-Induced delay, noise, and interconnect planarization implications of fill metal in nanoscale process technology”, IEEE Trans. on VLSI Systems, Vol. 18, No. 3, pp. 378-391, March.
[8]. A. Roy, J. Xu, and M.H. Chowdhury. (2010). “Analysis of the impacts of signal slew and skew on the behavior of coupled RLC Interconnects for different switching patterns,” IEEE Trans. on very large scale integration (VLSI) systems, Vol. 18, No. 2, pp 338-342, February.
[9]. J. Jang, S. Xu, W. Burleson. (2005).“Jitter in Deep Submicron Interconnect,” Proc. of the IEEE Computer Society Annual Symposium on VLSI New Frontiers in VLSI Design (ISVLSI'05), pp 84-89
[10]. T. Xia and D. Mu. (2010). “High speed interconnect data dependent jitter analysis,” Microelectronics Journal, Vol.41, pp. 371–379, April.
[11] . Y. I. Ismail, E. G. Friedman and J. L. Neves. (2001). “Exploiting the on-chip inductance in high-speed clock distribution networks,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 6, pp. 963-973.
[12] . Y. Cao, X. Huang, N. H. Chang, S. Lin, O. S. Nakagawa, W. Xie, D. Sylvester, and C. Hu. (2002). “Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion,” IEEE Trans. on VLSI Systems, Vol. 10, No. 6, pp. 799–805, Dec.
[13]. K. Banerjee and A. Mehrotra. (2001). “Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling”, Proc. IEEE Symp. VLSI Circuits, Kyoto, Japan, pp. 195-198.
[14]. Predicitive Technology Model, Online: http:// ptm.asu.edu.
[15]. MOSIS Service for HSPICE models, 2009. Online: http://www.mosis.org.
[16] B.K. Kaushik, S. Sarkar, R.P Agarwal, and R.C.Joshi (2006). “Cross-talk analysis and repeater insertion in interconnects,” Microelectronics International, Vol. 23, No.3, pp.55-63.
[17]. Pamunuwa, D., Zheng, L.R. and Tenhunen, H. (2003). “Maximizing throughput over parallel wire structure in the deep submicrometer regime”, IEEE Trans Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 2, pp. 224-243.
[18] Khanna, G., Sharma, P., Chandel, R. and Sarkar, S. (2008). “ Cross-talk mitigation in coupled VLSI interconnects”, Proc. 12th IEEE Sym. on VLSI Design and Test, Bangalore, India, pp. 364-374.
[19]. C. Park, J. P. John, K. Klein, J. Teplik, J. Caravella, J. Whitfield, K. Papworth, and S. Cheng, (1995) “Reversal of temperature dependence of integrated circuits operating at very low voltages,” Proc. [1]. IEDM Conf. pp. 71-74.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.