Analog-to-digital converters (ADCs) have been an essential part of many systems employed in mission critical applications. Their fault tolerance has been an increasingly important issue. The notion of fault tolerance includes fault detection (or testing). Automatic test equipment (ATE) has been extensively used to perform sophisticated testing of ADCs. However, ATE can not be utilized in the field due to extremely high cost. In addition, the bandwidth of the ATE is normally lower than the bandwidth of the ADC being tested, which makes it difficult to accomplish at-speed testing requirements. It is important, therefore, to embed test hardware into ADC itself. The methods employed at ATE are complex and inconvenient for built-in realization. More advantageous are the methods exploiting accumulation of output responses. The size of the accumulator depends on the number of responses. In order to achieve greater fault coverage, this number is kept large, complicating the implementation. On the other hand, signature analysis used in digital systems testing is well suited for compaction of “lengthy” responses, and it is characterized by small hardware overhead and low aliasing probability. In this work, we apply a signature analysis principle for the compaction of output responses of an ADC. The permissible tolerance bounds for a fault-free ADC are determined, and the aliasing rate is estimated. Examples are given.